Various types of electronic memory have been developed in recent years. Some exemplary memory types are electrically erasable programmable read only memory (EEPROM) and electrically programmable read only memory (EPROM). EEPROM is easily erasable but lacks density in storage capacity, whereas EPROM is inexpensive and denser but is not easily erased. “Flash” EEPROM, or Flash memory, combines the advantages of these two memory types. This type of memory is used in many electronic products, from large electronics like cars, industrial control systems, and etc. to small portable electronics such as laptop computers, portable music players, cell phones, and etc.
Flash memory is typically made up of an array of floating gate transistors, commonly referred to as memory “cells.” One or more bits of data are stored as charge by each memory cell. For example, dual bit memory devices use a silicon-oxide-nitride-oxide-silicon (SONOS) type architecture in which a lower layer of silicon oxide is formed over a semiconductor substrate that is typically silicon. A layer of silicon nitride is formed on the lower layer of silicon oxide, an upper layer of silicon oxide is formed on the layer of silicon nitride and a layer of an electrically conductive material is formed on the upper layer of silicon oxide. The combination of the lower silicon oxide layer, the silicon nitride layer, and the upper silicon oxide layer are capable of trapping charge and are commonly referred to as a charge trapping dielectric structure. It should be noted that the charge trapping structure is defined as an ONO stack. When more than one bit of information is stored in the charge trapping structure, the memory device is referred to as a dual bit memory device. Bit lines are typically formed in the portion of the semiconductor substrate that is below the charge trapping structure and word lines may be formed from the layer of electrically conductive material that is disposed on the charge trapping structure. In a dual bit memory device, two bits are stored per cell by biasing the bit line, the word line, the source, and the drain of the memory cell such that a bit and a complementary bit are stored. This arrangement enables flash memory cells to be manufactured efficiently and economically.
FIG. 1 shows a conventional memory cell. In a conventional flash memory fabrication process, the tunnel oxide, the charge-trapping layer, and top charge block oxide 101 (e.g., oxide-nitride-oxide ONO layer) and one or more polysilicon layers 102 are formed before the shallow trench isolation (STI 103) definition. It should be noted that the nitride layer can be comprised of nitride, silicon rich nitride, a combination of nitride on top of silicon rich nitride or multiple layers with different percentages of silicon content. After the STI 103 formation, another polysilicon layer can be deposited on the previous polysilicon layer. Subsequently, the word line is defined. Unfortunately, this conventional approach produces sharp corners 104-105 because the nature of the STI process produces near vertical sides. These sharp corners directly contribute to device degradation in performance and reliability.